Dynamic random access memories (DRAM) are useful for maximizing the number of bits stored per unit surface area. In particular, a single transistor (1T) DRAM cell includes a single MOS transistor, also referred to as a pass transistor or an access transistor, which is connected to a word line which is used to switch the pass transistor on or off to thereby couple or decouple a bit line to a storage capacitor. When the storage capacitor is charged to a predetermined Voltage, the memory cell stores a “1” state. When the storage capacitor is charged to a lower predetermined Voltage, typically ground, the memory cell stores a “0” state.
The Voltage stored, e.g., as a “1” state in the memory cell decays over time to a lower “0” state Voltage (e.g., ground Voltage) through various leakage mechanisms. Unlike the charge replenishing process for static RAM, the only way to maintain the information in DRAM is by periodically reading and rewriting the data through a “refresh” operation. Avoiding current leakage and thereby maintaining charge retention in a DRAM cell is extremely important for scaling down memory cell size.
Several leakage mechanisms can affect the stored charge in DRAM cells including junction leakage, pass transistor threshold leakage and leakage through the storage capacitor dielectric as well as other parasitic leakage paths. In particular, prior art memory 1T DRAM memory cells, including for example, planar storage capacitors have unacceptable charge retention times for future applications at required memory cell densities.
Therefore, there is a continuing need in the DRAM processing art to develop a DRAM memory cell with improved charge retention time and reduced size while avoiding undue manufacturing cost.
It is therefore among the objects of the invention to provide a DRAM memory cell with improved charge retention time and reduced size while avoiding undue manufacturing cost, in addition to overcoming other shortcomings and deficiencies of the prior art.